Cadence Tutorial: Silicon Logic Gates (Iowa State University EE330 Lab 4)

The emergence of electronics has revolutionized many aspects of our daily lives. Electronics are used in or used to create nearly every product purchased today. Whether it is the electronics that run the newest video game system or those used to keep a person with a pacemaker alive, they have all added to the quality of life we enjoy today. A large number of electronic circuits are digital logic circuits. Today a basic digital logic circuit will be designed to implement a basic Boolean function.
This is the fourth lab of the introduction to integrated electronics course (EE 330) at Iowa State University. In this lab a Boolean function will be implemented in silicon using the Cadence design suite of software. Parameterized cells or p-cells will be introduced and the entire design flow for integrated electronics will be completed for a basic logic design. This instructable is meant specifically for the integrated electronics class at Iowa State University, but others may find it useful. It assumes the user has a basic knowledge of how to use Linux and Cadence and basic knowledge of integrated electronics.

This lab will guide the user through the creation of an inverter using p-cells.. The reader will then be asked to create their own 3-input NAND gate design. The reader will be asked to design a schematic and layout for the 3-input NAND gate. The deliverables from this lab will include the completed schematic, layout, and proof of verification of both the inverter and the 3-input NAND gate.

The lab should be mostly completed after the three hour lab period, but it may be necessary to spend an hour or two outside of the lab period to complete the lab and prepare a lab report. After finishing this lab you will be on your way to having the fundamentals of digital logic design and layout mastered!

 

Materials List

Before starting this lab you will need to have the following materials:

• Completed pre-lab

The pre-lab is available at:
http://class.ee.iastate.edu/ee330/labs/EE%20330%20Lab%204%20Spring%202011%20Prelab.pdf

• A computer with access to the Cadence software suite

The class lab room, 2046 ECpE Addition, is the ideal location for working on the lab. However the Cadence software is also available from almost any computer remotely. The remote connection can be established in both Linux and Windows. In the Windows environment, you can connect to Linux server using NX Client. All windows machines in Coover hall have NX client installed and the client can be downloaded at http://www.nomachine.com/download.php. The servers can also be accessed through SSH on Linux machines. The list of servers with Cadence installed on them is available at

• Textbook for reference (Optional)

N. Weste and D. Harris , CMOS VLSI Design – A Circuits and Systems Perspective, Fourth Edition, Addison Wesley, 2011

Step 1: Setup Cadence

The Cadence environment was setup in the first lab of the semester. If this is not complete or you are using a new project directory and you are using an Iowa State computer you will need to follow the tutorial available at: http://wikis.ece.iastate.edu/vlsi/index.php/Cadence_6.1_Setup

Creating a new Library:
1. Change directory to your project folder by typing "cd {PROJECT DIR}" into a terminal

• {PROJECT DIR} is the lab project directory that was created in lab 1. This is the directory that Cadence should always be ran from and which contains each library folder.

2. Start Cadence by typing in “virtuoso &” into the terminal
3. Create a new library by going to File ⇒ New ⇒ Library

• The menu bar is located at the top of the library manager screen

4. Name your Library "Lab 4" [fig 1]
5. Click OK
6. Select "Attach to an existing technology library" [fig 2]

• This is the technology library that defines the design rules, device models, and fabrication parameters. It also provides a number of useful standard cells.

7. Click OK
8. Select "NCSU_Techlib_ami06" [fig 3]
9. Click OK

Now the new library will show up in the Library Manager screen and is ready to have cells added.

Step 2: Design an Inverter Schematic

Create a Schematic for your inverter:

1. Select "Lab4" Library created in the last step
2. Create a new cell view by going to File ⇒ New ⇒ Cell View
3. Name the Cell View "Inverter" [fig 1]
4. Set the view to be "schematic" [fig 1]
5. Select the type as "schematic" from the drop down menu [fig 1]
6. Click OK
7. Open the schematic by selecting it from the library manager [fig 2]

A. Select the "Lab4" library in the library manager
B. Select the "Inverter" cell view from the library manager
C. Double click the "schematic" view

8. Insert an instance of an NMOS from the "NCSU_Analog_Parts" library

A. Select Create ⇒ Instance or hit the "i" key [fig 3]
B. Click "Browse" next to the Library entry blank [fig 4]
C. Select "NCSU_Analog Parts" library from the drop-down menu [fig 5]
D. Select "N_Transistors"
E. Select "nmos4" [fig 6]
F. Place NMOS instance in the schematic window [fig 7]

9. Insert an Instance of a PMOS from the "NCSU_Analog_Parts" library [fig 8]

• The procedure is the same as that in step 8, except "P_Transistors" should be selected followed by the "nmos4” cell. If the instantiation form contains the information for the NMOS the cell field can be changed to "pmos4" instead of browsing for the view.
• Make sure to change the size of the PMOS to 4.5um. In order to achieve equal rise and fall times the size of the PMOS transistors in a pull-up network must be three times minimum size. Minimum size in our process is 1.5um. The electron mobility, µp, of a PMOS is 1/3 that of an NMOS, leading to the speed and effective resistance differences between the two transistor types.

10. Place Power Pins

A. Select Create ⇒Pin... or hit the "p" key
B. Enter "Vin Vout" in the Name of the pin instantiation form [fig 9]
C. Select “InputOutput” as the Direction [fig 9]
D. Click in the schematic window to place the Vdd pin [fig 10]

• The Vdd pin should be placed close to the source of the PMOS

E. Click a second time in the schematic window to place the Vss pin [fig 10]

• The Vdd pin should be placed close to the source of the NMOS

11. Place the Input Pin

• The Input Pin should be placed to the left near the gates of the Transistors [fig 12]
• The "Direction" of the input pin should be set to "input". [fig 11]

12. Place the Output Pin

• The output pin should be placed to the right near the drains of the transistors. [fig 12]
• The "Direction" of the output pin should be set to "output".

13. Wire the inverter [fig 13]

A. Select the wire tool by going to Create ⇒Wire (narrow) or by hitting "w"
B. Click a pin or transistor and then click another to connect the two

• The PMOS and NMOS drains are wired to the output
• The PMOS source and bulk are wired to Vdd
• The NMOS source and bulk are wired to Vss
• The PMOS and NMOS Gates are wired to the input

The completed inverter schematic is now ready for layout. [fig 13] Be sure to properly document your work and prepare screen shots for your lab report.

Step 3: Layout an Inverter Using P-cells

Next we will create the layout of the inverter using parameterized cells or p-cells. P-cells are premade layouts of a cell that have parameters that can be adjusted to change the layout. In our case we will be using transistor p-cells and adjusting the width parameter of the cell to create the layout of the NMOS and PMOS transistors. Using p-cells will save a lot of time over laying out each transistor individually.

1. Create a new layout cell view for the inverter [fig 1]

A. Set the view to layout
B. Click OK

• The layout window will open with a blank layout screen
• On the left is the layers toolbar from which you will select which design layer you are currently working with. The layers menu also controls which layers are selectable and which are visible. [fig 2]

2. Instantiate an NMOS p-cell Layout

• P-cells are pre-made layouts that can be altered to meet the designer’s needs by changing the component’s parameters. Examples of two PMOS transistor p-cells are shown in figure 3. The left p-cell has a width of 1.5 um and the p-cell on the right has a width of 4.5um. [fig 3]

A. Select Create ⇒Instance... or hit the "i" key
B. Set the library to “NCSU_TechLib_ami06” [fig 4]
C. Set the cell to “nmos” [fig 4]
D. Set the view to “layout” [fig 4]
E. Check the model name is set to “ami06N” [fig 4]
F. Set the width to 1.5um [fig 4]
G. Place the cell in the layout window near the origin

3. Instantiate a PMOS p-cell layout

A. Select Create ⇒Instance... or hit the "i" key
B. Set the library to “NCSU_TechLib_ami06” [fig 5]
C. Set the cell to “pmos” [fig 5]
D. Set the view to “layout” [fig 5]
E. Check the model name is set to “ami06P” [fig 5]
F. Set the width to 4.5um [fig 5]
G. Place the cell in the layout window directly above the NMOS cell

• The NMOS and PMOS cells will show up as cell level representations [fig 6]

4. Hit shift key and “F” key simultaneously to change to layer view

• The layout’s layers will become visible [fig 7]
• Pressing the ctrl key and the “F” key simultaneously will return the view to the cell component level and abstract away the underlying layout design.

5. Reposition the NMOS cell [fig 8]

• Center the polysilicon (red poly layer) gate of the NMOS and PMOS with each other

A. Click and hold in the center of the NMOS cell
B. Drag the NMOS cell into position

6. Connect the NMOS and PMOS Gates [fig 8]

A. Select Create ⇒ Shape ⇒ Rectangle or press the “R” key
B. Select “poly” from layers toolbar
C. Draw a rectangle between the gate of the NMOS and the gate of the PMOS

• Overlapping polygons on the same layer has no effect on the layout.

7. Add PMOS bulk connection [fig 11]

A. Select Create ⇒ Via…
B. Select “NTAP” for the via definition field [fig 9]
C. Place the PMOS bulk connection near the PMOS attached to the green n-well

• The bulk terminal is the n-well the PMOS is placed inside.

8. Add NMOS bulk connection [fig 11]

A. Select Create ⇒ Via…
B. Select “M1_P” for the via definition field [fig 10]
C. Place the NMOS bulk connection the left or right of the NMOS transistor

• The bulk terminal of the NMOS is the p doped substrate.

9. Add via to connect input metal layer to the polysilicon gates [fig 13]

A. Select Create ⇒ Via…
B. Select “M1_POLY” for the via definition field [fig 12]
C. Place the NMOS bulk connection the left or right of the NMOS transistor

• The input should start on metal one so it is easy to route the inverter. The via connects the metal input wiring to the polysilicon gates.

10. Wire the input [fig 13]

A. Connect the input via to the polysilicon gate

• Use a poly rectangle for this connection

B. Wire the input to the leftmost edge of the cell.

• Use Metal 1 to wire the input via to the left edge.

11. Wire the output [fig 13]

• The output will be wired to the rightmost edge of the cell.
• The output must connect the right terminal (drain) of each transistor to the output.

12. Wire the power supply lines [fig 13]

• Vdd must be drawn as a wire on metal1 across the top of the cell.
• Vdd must connect to the left terminal (source) of the PMOS and the bulk of the PMOS.
• Vss must be drawn as a wire on metal1 across the bottom of the cell
• Vss must connect to the left terminal (source) of the NMOS and the bulk of the NMOS.

13. Add power pins [fig 14]

A. Select Create ⇒ Pin…
B. Set terminal names to "Vdd Vss"
C. Select “InputOutput” as the I/O type
D. Select metal1 in the layers toolbar
E. Add Vdd pin to top power supply wire
F. Add Vss pin to bottom power supply wire

14. Add input Pin

• Pin should will be on metal1 layer
• Pin will have “Input” I/O type

15. Add output Pin

• Pin should will be on metal1 layer
• Pin will have “Output” I/O type

The layout is now ready to be verified.

Step 4: Verify Layout

The final step of designing an inverter is to verify that the component was designed correctly. There are two main tests that need to be completed to verify the design. The first is the design rule check or DRC. The DRC checks to make sure that none of the design rules that dictate how the layout can be drawn have been violated. These rules include many different rules, but a few common types include minimum spacing requirements, minimum feature size, and area requirements. The second test that must be completed is the layout versus schematic or LVS test. This test compares the layout that is designed and checks that it matches the schematic. In order to pass this test the schematic must have equivalent device sizes and parameters and the layout must be electrically equivalent to the schematic.

DRC Test:

1. Run the DRC check [fig 2]

A. Select Verify ⇒ DRC…
B. Click OK

2. Check DRC output in command line

• Almost all layouts will encounter an error the first time the DRC is ran
• The DRC will report errors in the command window [fig 3]
• The DRC will report no errors found if successful [fig 6]

3. Locate any errors in layout

• The errors are marked using white markers in the layout window [fig 4]
• The markers can be explained by selecting Verify ⇒ Markers ⇒ Explain and then clicking on the marker. A textbox will pop up with a brief explanation of the error. [fig 5]

4. Correct the error

• Depending on the type of error there will be different solutions.
• Most of the errors are geometric in nature and require the layout to be reconsidered.
• Often moving one rectangle slightly will fix an error.

5. Reiterate DRC test and error correction until there are no errors

• A successful DRC will be reported as 0 errors in the command window. [fig 6]

 

LVS Test:

6. Extract the circuit [fig 7]

A. Select Verify ⇒ Extract
B. Click OK

• Extraction estimates the circuit parameters of the schematic based on the layout
• Must be completed before a LVS test can start
• The LVS actually compares the extracted view to the schematic rather than the actual layout

7. Start LVS [fig 8]

A. Select Verify ⇒ LVS…
B. Select inverter schematic view
C. Select inverter extracted view
D. Click run

8. Wait for the LVS to complete

• When the LVS is complete a window will pop up with the status of the LVS test. If the windoe says the “Net-lists” match that indicates the schematic and layout are simailar
• If the window reports the LVS failed to run check that the directions in step 7 were followed properly. A common mistake is to choose the layout rather than the extracted view.

9. Examine the output file

A. Select Verify ⇒ LVS…
B. Select Output [fig 8]
C. Examine output file for errors

• Check for “Net-lists match”
• Look for Error flags
• The number of devices should be equivalent in the schematic and extracted views.

10. Document success

• Take screenshots of both verification tests for the lab report

Step 5: Design a 3 Input NAND Logic Gate

The next part of the lab is a design exercise. The reader will design a three input NAND gate independently.

1. Design the schematic

• The three input NAND will have three transistors in series. In order to have equal rise and fall times the size of 3 transistors in series must be 3 times larger.
• Sizing the transistors properly is essential for a correct schematic.

2. Design the layout

• Explore the use of fingers and multiplier parameters to create series and parallel transistor combinations
• Minimize the area of the layout

3. Verify the layout

• Verify both DRC and LVS tests

Deliverables:

• Schematic
• Layout
• Successful DRC output
• Successful LVS output

Each deliverable must be properly documented and presented to the teaching assistant before the lab report due date.

Step 6: Conclusion

At the end of this lab the schematic and layout of an inverter along with the schematic and layout of a 3 input NAND gate should be completed. Each of these pieces is a vital building block for building digital logic circuits. Make sure that all work has been properly documented and explained in your lab report. The lab report explanation should be is a large portion of your grade for the lab and should be thorough enough to demonstrate your understanding of the process.

This lab is the first step of many steps required to create a fully functional integrated circuit. The logic gates developed in this lab will be used in the next lab to assemble a Boolean function and make a final layout for the Boolean function. The next lab also explains how to simulate the final circuit to verify that the original schematic is functionally correct for the Boolean function given. This will lead to the final product, a design for an integrated digital logic circuit! This design could then be taken and fabricated at any foundry that has the ami06 process available.